Operating Heterogeneous Systems at Scale

The continuity of Moore’s law provides chip designers with an ever growing amount of transistors. These can be used to put more cores on a single chip in order to gain performance through parallelism. However, this is not the most energy efficient approach to speed up computation. Yet, the power budget is a limiting factor for a chip’s obtainable performance. Specialized accelerators provide better energy efficiency and execute the tasks they are designed for faster than traditional multicores. Already existing approaches like integrated GPUs, cryptographic co-processors or heterogeneous multicores like ARM big.LITTLE confirm this observation. In these systems the processing elements (PE) are typically connected via a network-on-chip (NoC), which shifts their internal communication characteristics towards those of distributed systems. Even today’s multicore systems possess such properties when looking at their memory accessibility. The memory modules are split across the cores, hence accessing a memory location connected to a remote core is a remote operation using a different core’s memory controller. However, the true nature of the chip’s structure is not presented to the OS. Revealing the NoC to the OS enables a new approach to provide isolation.